1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming replacement gate structures on FinFET devices and the resulting devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a traditional FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate cap 20. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 10. The fins 14 have a three-dimensional configuration: a height 14H, a width 14W and an axial length 14L. The axial length 14L corresponds to the direction of current travel, i.e., the gate length (GL) of the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 is the channel region of the FinFET device 10. In a conventional process flow, the portions of the fins 14 that are positioned outside of the spacers 18, i.e., in the source/drain regions of the device 10, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes to grow additional semiconductor material on the fins in the source/drain regions of the device 10.
FIG. 1B depicts a simplistic plan view of the traditional FinFET device comprised of three illustrative fins 14. A cross-sectional view of the device 10 taken through the gate structure 16 is depicted in FIG. 1C. With reference to FIG. 1C, the device 10 includes a layer of insulating material 22 positioned between the fins 14, another layer of insulating material 24 that is positioned above the gate cap layer 20, and a gate contact structure 28 that is conductively coupled to the gate structure 16. The device 10 depicted in FIG. 1C is a tri-gate (or triple gate) FinFET device. That is, during operation, a very shallow conductive region 26 (shown only on the middle fin in FIG. 1C) will be established that provides a path or channel for current to flow from the source region to the drain region. The conductive region 26 forms inward of the side surfaces 14S and below the top surface 14T of the fins 14. As depicted, the overall gate length (GL) of the FinFET device 10 and the overall gate width (GW) of the FinFET device 10 are all oriented in a direction that is substantially parallel to a horizontal surface 12A of the substrate 12.
For many early device technology generations, the gate electrode structures of most transistor elements were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 14-32 nm, gate structures comprised of a high-k gate insulation layer (k value of 10 or greater) and one or more metal layers, a so-called high-k dielectric/metal gate (HK/MG) configuration, have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed.
The formation of gate structures on FinFET devices presents several unique challenges. Typically the fins 14 are formed by performing an etching process through a patterned hard mask layer to define a plurality of trenches in a substrate. The portions of the substrate 12 covered by the patterned hard mask layer are the fins 14. A typical hard mask layer is comprised of a layer of thermally grown silicon dioxide (pad oxide) formed on the substrate 12 and a layer of silicon nitride (pad nitride) formed on the pad oxide layer. The pad nitride and pad oxide layers are then patterned using photolithographic and etching techniques to thereby define the patterned hard mask layer. In today's advanced generation devices, the fins 14 for FinFET devices are very thin, and thus easily damaged if the patterned hard mask is not thick enough. Additionally, if the pad oxide portion of the hard mask layer is too thick, then it is very hard to insure complete removal of the pad oxide portion and, thus, difficult to form tri-gate (triple-gate) FinFET devices. Normally, the process steps, i.e., the etching process module or steps that are performed to etch the substrate 12 to define the fins 14, are not readily transferable when there is a change to the structure of the fins 14. That is, if a parameter, such as fin height, fin width or hard mask thickness, is changed, then the entire etching process module needs to be re-worked, i.e., the old etching process module cannot readily be employed on fins 14 with different physical parameters. This results in a tremendous consumption of research and development time and resources to produce a new etching process module that can be employed in the fabrication facility to form the newly designed fins. These problems may be even more problematic as it relates to the formation of replacement gate structures on FinFET devices.
Another problem encountered with traditional fabrication techniques used to manufacture FinFET devices is related to topography control. Typically, after the trenches are formed that define the fins 14, a recessed layer of insulating material 22 is formed in the trenches between the fins 14. Thereafter, a sacrificial gate insulation layer is thermally grown on the exposed portions of the fins 14 above the recessed layer of insulating material 22. Next, the material for the sacrificial gate, e.g., amorphous silicon, is blanket-deposited across the substrate 12 so as to over-fill the trenches. Given the topography of the fins 14 and the trenches, the upper surface of the deposited sacrificial gate material is uneven and must be planarized (by CMP) prior to formation of a material for the gate cap layer, e.g., silicon nitride. The planarization process is a timed process, i.e., the polishing process does not stop on another material layer. Thus, the thickness of the sacrificial gate material above the upper surface of the fins 14 is controlled by the duration of the polishing process. Any variation in the polishing rate and/or duration of this polishing process causes undesirable variation in the thickness of the sacrificial gate material. Such thickness variations can occur from wafer-to-wafer and/or from lot-to-lot and can create further manufacturing problems.
The present disclosure is directed to methods of forming replacement gate structures on FinFET devices and the resulting devices that may solve or reduce one or more of the problems identified above.